Cost-Effective buffered wormhole routing
ISPA'04 Proceedings of the Second international conference on Parallel and Distributed Processing and Applications
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A comparison is made among a large number of designs for the purpose of specifying low-cost yet cost-effective multicomputer network switches. Among the parameters varied are switching mode, number of lanes, buffer size, wraparound, and channel selection. Some assumptions we make are deterministic routing and small fixed-sized packets. We obtain results using two methods: i) RTL cycle-driven simulations to determine latency and capacity with respect to load, communication pattern, and packet size and ii) hardware synthesis to a current technology to find the operating frequency and chip area. These results are also combined to yield performance/area measures for all of the designs. One of the results is deeper understanding of virtual cut-through in terms of deadlock properties and the capability of dynamic load balancing among buffers. We find that lanes are even more likely to improve performance of virtual cut-through as wormhole networks, and that virtual cut-through routing is preferable to wormhole routing in more domains than may have been previously realized. Other results include finding that, after factoring in operating frequency, having more than two lanes per physical channel is not likely to be useful and various observations about the utility of varying buffer sizes.