Planar-adaptive routing: low-cost adaptive networks for multiprocessors
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Flexible and Efficient Routing Based on Progressive Deadlock Recovery
IEEE Transactions on Computers
A Performance Model for Duato's Fully Adaptive Routing Algorithm in k$k$-Ary n$n$-Cubes
IEEE Transactions on Computers
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
IEEE Transactions on Parallel and Distributed Systems
Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels
IEEE Transactions on Parallel and Distributed Systems
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Optimized Routing in the Cray T3D
PCRCW '94 Proceedings of the First International Workshop on Parallel Computer Routing and Communication
Design Trade-Offs of Low-Cost Multicomputer Network Switches
FRONTIERS '99 Proceedings of the The 7th Symposium on the Frontiers of Massively Parallel Computation
| Hi-index | 0.00 |
The cost-effectiveness of wormhole torus-networks is systematically evaluated with emphasis on new buffered-wormhole routing algorithms. These algorithms use hardwired datelines and escape channels to alleviate bottleneck and bubble problems caused by previous algorithms and so to improve the buffer efficiency with little hardware overhead. A two-part evaluation environment is developed consisting of a cycle-driven simulator for high-level measurements such as network capacity and an ASIC design package for low-level measurements such as operating frequency and chip area. This environment is used to demonstrate that the new routers are more cost-effective than their counterparts under various workload parameters.