Top-Down Design Using Cycle Based Simulation: an MPEG A/V Decoder Example

Authors:
Dale E. Hocevar;Ching-Yu Hung;Dan Pickens;Sundararajan Sriram
Affiliations:
-;-;-;-
Venue:
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
Year:
1998

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Cited 2

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Abstract

This paper presents a discussion of a top-down VLSI design approach which involves system level performance modeling, block level cycle based simulation, RTL/VHDL simulation and gate level emulation. An MPEG-2 Audio/Video decoder design example illustrates the use of this top-down approach. Most of the discussion concentrates on the concept of block level cycle based (BLCB) simulation. HW/SW co-design also played an important role in this work and our approach towards such co-design is discussed as well.