Synthesis of SEU-tolerant ASICs using concurrent error correction

  • Authors:

  • H. Hollander;B. S. Carlson;T. D. Bennett

  • Affiliations:

  • -;-;-

  • Venue:
  • GLSVLSI '95 Proceedings of the Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
  • Year:
  • 1995

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Abstract

We present a new design technique for the concurrent error correction of single event upsets in the memory elements of ASICs. The technique uses a single error correction/double error detection (SEC/DED) Hamming code to encode the content of the memory elements. The area and delay overhead and error-correction capability are optimized by partitioning the set of memory elements. Design experiments show our technique is feasible, and it can be applied to any ASIC technology.