Parallel logic simulation of VLSI systems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
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Explores the performance of three synchronous discrete-event simulation algorithms: the global clock algorithm, the conservative lookahead algorithm, and speculative computation. We examine the effects of granularity and present empirical data to illustrate at what granularity the algorithm has reasonable performance. We also investigate two techniques for decreasing both synchronization and load imbalance. In addition, we examine how various execution platforms impact the performance of the simulation, providing empirical data from a network of workstations and a shared-memory multiprocessor. The impact of shared computational resources on simulation performance is also explored. The simulated system is a network of queues connected in a torus topology.