Deadlock analysis in the design of data-flow circuits

Authors:
Chu S. Jhon;Robert M. Keller
Affiliations:
Electrical and Computer Engineering Department, University of Iowa, Iowa City, Iowa;Computer Science Department, University of Utah, Salt Lake City, Utah
Venue:
DAC '84 Proceedings of the 21st Design Automation Conference
Year:
1984

Citing 2
Cited 1

An Extensional Treatment of Dataflow Deadlock

Proceedings of the International Sympoisum on Semantics of Concurrent Computation
A Fundamental Tehoerem of Asynchronous Parallel Computation

Proceedings of the Sagamore Computer Conference on Parallel Processing

Yet another silicon compiler

DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference

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Abstract

One means of making VLSI design tractable is to proceed from a high-level specification of a circuit in terms of functionality, to the circuit level. A notable error which may occur in a top-down design starting with a data-flow graph representation of a circuit is a design inconsistency due to deadlock. This paper attempts to further develop the theoretical basis for algorithms which analyze the deadlock property of circuits on the basis of their data-flow graph representations. A systematic scheme to verify the absence of deadlock in data-flow graphs is also presented.