A data structure for MOS circuits
DAC '83 Proceedings of the 20th Design Automation Conference
MGX: An integrated symbolic layout system for VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
Deadlock analysis in the design of data-flow circuits
DAC '84 Proceedings of the 21st Design Automation Conference
Optimal layout of CMOS functional arrays
Optimal layout of CMOS functional arrays
A case study in silicon compilation software engineering, HVDEV high voltage device layout generator
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Automated layout synthesis in the YASC silicon compiler
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Principles of the SYCO compiler
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Behavioral Model Synthesis with Cones
IEEE Design & Test
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In this paper, we describe the YASC high-level silicon compiler which synthesizes compact chip layouts from hierarchical behavioral descriptions. A logic synthesis procedure generates sets of Boolean equations, including multi-phase clocks and any necessary interface logic. A novel technique for layout generation yields cells whose densities approach hand-crafted designs. Two-layer metal NMOS and CMOS technologies are supported, with flexible design rules. In addition to layout synthesis, logic, schematic and graph diagrams are generated directly from a powerful internal data base. The compiler, which runs under the UNIX^^ operating system, includes a menu-driven multi-windowing user environment.