Performance potential of communications interface processors

Authors:
C. M. Woodside
Affiliations:
Department of Systems and Computer Engineering, Carleton University, Ottawa, Canada
Venue:
SIGCOMM '83 Proceedings of the eighth symposium on Data communications
Year:
1983

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Abstract

Interface processors are being developed in hardware and firmware for communications protocols at higher and higher levels (HDLC, X.25, Ethernet ...), for smaller and smaller host systems. How far this process will go depends on the driving factors of increased performance and simpler implementation of the systems which use the protocols. A simplified performance model with parameters, which encompasses a large part of all systems using communications, is used to find those parameter combinations offering various degrees of performance improvement. The results can be used to approximately distinguish those cases which will provide the market for performance improvement via higher-level interface processors.