A performance model for hardware/software issues in computer-aided design of protocol systems

Authors:
C. M. Woodside;R. Montealegre;R. J. A. Buhr
Affiliations:
Department of Systems & Computer Engineering, Carleton University, Ottawa, Canada;Department of Systems & Computer Engineering, Carleton University, Ottawa, Canada;Department of Systems & Computer Engineering, Carleton University, Ottawa, Canada
Venue:
SIGCOMM '84 Proceedings of the ACM SIGCOMM symposium on Communications architectures and protocols: tutorials & symposium
Year:
1984

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Abstract

Protocol execution can run into bottlenecks which are due to implementation decisions rather than to the protocol rules. The performance effects of processor saturation, buffer management strategy, allocation of functions between host and front-end, and hardware-software interactions due to special hardware attributes can, in principle, be predicted at the design stage by analytic performance models. The paper describes the process of construction of such a model for the data transfer stage of a simple transport protocol resembling an OSI class 4 protocol, including queueing for critical sections which protect the buffer pools and connection state information. The model is part of a computer-aided design process for communications systems, currently under development.