The Apiary network architecture for knowledgeable systems
LFP '80 Proceedings of the 1980 ACM conference on LISP and functional programming
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Critical issues in mapping neural networks on message-passing multicomputers
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
The de Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI
IEEE Transactions on Computers
Optimal Distance Networks of Low Degree for Parallel Computers
IEEE Transactions on Computers
Optimal Layouts of Midimew Networks
IEEE Transactions on Parallel and Distributed Systems
The general matrix multiply-add operation on 2D torus
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Task mapping in rectangular twisted tori
Proceedings of the High Performance Computing Symposium
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The twisted torus processing surface, introduced and analyzed by Martin,1,2 is extended to contain a double twist and then mapped into a two-dimensional network suitable for implementation on a VLSI wafer. The result is a homogeneous, isotropic multiprocessor configuration without boundaries. Every processor has four nearest neighbors, and the interconnections between all pairs of processors are of approximately equal length. Special attention is given to mapping binary trees onto the processor array. Most divide-and-conquer-type problems will distribute themselves relatively uniformly over all available processors. Nine building blocks are introduced that will permit making doubly twisted torus arrays of arbitrary sizes.