Local Microcode Compaction Techniques
ACM Computing Surveys (CSUR)
Towards an efficient, machine-independent language for microprogramming
MICRO 12 Proceedings of the 12th annual workshop on Microprogramming
Methods of compacting microprograms
Methods of compacting microprograms
Efficient hardware for multiway jumps and pre-fetches
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
JAM—just another microsequencer
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
Branch merging for effective exploitation of instruction-level parallelism
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Resource-Constrained Software Pipelining
IEEE Transactions on Parallel and Distributed Systems
Critical path reduction for scalar programs
Proceedings of the 28th annual international symposium on Microarchitecture
Increasing the instruction fetch rate via block-structured instruction set architectures
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Hardware implementation of a general multi-way jump mechanism
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Very long instruction work architectures and the ELI-512
25 years of the international symposia on Computer architecture (selected papers)
Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures
International Journal of Parallel Programming
Generalized Multiway Branch Unit for VLIW Microprocessors
IEEE Transactions on Parallel and Distributed Systems
A microsequencer architecture with firmware support for modular microprogramming
MICRO 15 Proceedings of the 15th annual workshop on Microprogramming
MICRO 15 Proceedings of the 15th annual workshop on Microprogramming
Very Long Instruction Word architectures and the ELI-512
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Applications of pipelining to firmware
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
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A scheme is developed by which multiway microprogram jumps may be made to any of 2n next possible microinstructions as a function of any selection of n 1 logically independent tests. An efficient method of binding microinstructions to memory locations allows this to be done at very low cost, both in terms of speed and hardware. Independent simultaneous tests are a necessity if horizontally microcodable machines are to continue to get wider, since algorithms presumably have fixed operations/tests ratios. This scheme will give parallelizers for such machines maximum flexibility in rearranging flow control.