Analysis of actual fault mechanisms in CMOS logic gates

  • Authors:
  • Glenn R. Case

  • Affiliations:
  • -

  • Venue:
  • DAC '76 Proceedings of the 13th Design Automation Conference
  • Year:
  • 1976

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Abstract

An analysis of failure modes in CMOS logic gates is presented. An example 3-input NAND gate is analyzed in detail and the ramifications of its failure modes are discussed.