An interactive logic activity modelling program

• Authors: H. B. Rigas;H. B. Jacoby;V. B. Hunt
• Venue: ACM '72 Proceedings of the ACM annual conference - Volume 2
• Year: 1972

Simulation of logic networks can be a valuable tool in such areas as teaching the principles of logic design, investigating hardware implementation of arithmetic algorithms, and verifying the validity of test sequences in fault diagnosis of various types of networks to mention only a few possible applications. To be useful for a large number of problems in these classes, the simulator should be both flexible in its application and convenient to use. A system is described here which allows a user to obtain realistic digital network simulations in batch mode, interactively from a teletype or graphics terminal or through some combination of these modes. The simulator does account for propagation time through discrete logic components but the timing facility may be over-ridden. A hierarchy of networks may be built up and saved, thus allowing gradual fabrication of a complete system hardware simulation.