Time flow mechanisms for use in digital logic simulation
WSC '71 Proceedings of the 5th conference on Winter simulation
DAC '75 Proceedings of the 12th Design Automation Conference
| Hi-index | 0.00 |
This paper describes the development of element models (basic gates and flip-flops) for use in a multi-modal, assignable-delay logic simulator known as TEGAS2. The basic mechanism of this event-driven simulator is first described, together with the operation of the three basic simulation modes (nominal-delay two-value simulation, nominal-delay three-value simulation, and three-value simulation using an ambiguity region to provide race and hazard detection). The criteria used in developing the element models were: 1) The element should operate in a consistent manner for all simulation modes; 2) A basic set of circuit building blocks should be available; 3) The element evaluation should be relatively rapid; and 4) The set of element routines should be extensible. In order to discuss the above philosophy in detail, the desired operation of the And element is first described for each simulation mode. Equations are then derived from this description, and finally the Fortran statements are obtained. The handling of memory elements in a simulator poses a special problem. A Delay (“D”) flip-flop is used as an illustration of memory element modeling techniques; again, the development starts with a verbal description of the operation and arrives at the Fortran statements for the various simulation modes. A level-triggered master-slave J-K flip-flop is then used as a vehicle for a general discussion of the problems associated with more complex memory elements. A brief description is also given of the clocked S-R models used in the system.