A systolic (VLSI) array using RNS for digital signal processing applications

  • Authors:

  • M. A. Bayoumi;G. A. Jullien;W. C. Miller

  • Affiliations:

  • -;-;-

  • Venue:
  • CSC '84 Proceedings of the ACM 12th annual computer science conference on SIGCSE symposium
  • Year:
  • 1984

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Abstract

A high speed one-dimensional systolic array is proposed for implementing finite impulse response (FIR) digital filters.The structure is completely pipelined, that is, the throughput rate (bits/sec.) is independent of the filter length.Residue Number System (RNS) is used for implementing the mathematical operations.RNS has a parallel nature where the arithmetic operations are performed independently for each modulus which enhances the system speed.VLSI is used as a fabrication medium which supports the modular implementation.The building block unit is a multi-look-up table module which has two possible configurations.The area-time complexity of an FIR structure is analyzed based on an RNS computational model.