FPGA-based implementation of safe Petri nets models
AMCOS'05 Proceedings of the 4th WSEAS International Conference on Applied Mathematics and Computer Science
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Simulation of systems for the control of large numbers of objects such as traffic flows, network message traffic, etc is CPU intensive and may require inordinately long runs on conventional sequential processors. This work describes the Achilles re-configurable processor and techniques for programming it to carry out Petri Net simulations. Achilles is an innovative 3-dimensional stack of FPGAs. The 3-D arrangement allows (a) a large number of FPGAs to fit in a small volume, (b) a large degree of flexibility in the way individual devices are interconnected, (c) interconnection with one or more hosts with host-Achilles bandwidth being scaled up to meet requirements and (d) individual stacks to be connected together in a wide variety of patterns so that the computing power of the stack may be scaled as necessary.Bandwidths between the stack and a PC host have been measured at over 30Mbytes/second in the first proto-type of the stack: the interconnection is capable of transfer-ring data at PCI bus speeds with the newer, faster FPGAs used in the second prototype currently under construction. This architecture is particularly suitable for Petri Net simulations as hundreds of places in a net can be simultaneously active - reducing by orders of magnitude the time necessary for simulations.