Design of an Adaptive Architecture for Energy Efficient Wireless Image Communication
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Mixing ATPG and property checking for testing HW/SW interfaces
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Design of an adaptive architecture for energy efficient wireless image communication
Embedded processor design challenges
A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Fault Models and Test Generation for Hardware-Software Covalidation
IEEE Design & Test
Verification of a Complex SoC: The PRO3 Case-Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
| Hi-index | 0.00 |
The availability of reusable IP-cores, increasing time-to-market and design productivity gap, and enabling deep sub-micron technologies have led to core-based system-on-chip (SoC) design as a new paradigm in electronic system design. Validation of these complex hardware/software systems is the most time consuming task in the design flow. In this paper, we focus on developing an efficient interface-based validation methodology for core-based SoC designs. In SoCs designed with pre-validated IP cores, the verification complexity can be significantly alleviated by concentrating on the integration of the cores in the system, rather than the complete SoC. In this paper, we investigate typical interface problems that arise in integrating cores in an SoC, and classify these problems into different categories. Based on the classification of these interface problems, we introduce an interface-based validation methodology. Finally, we demonstrate the effectiveness of the proposed methodology using an example image compression SoC that we are developing.