Fault Models and Test Generation for Hardware-Software Covalidation
IEEE Design & Test
A framework for systematic validation and debugging of pipeline simulators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Buffer-Oriented Microarchitecture Validation (BMV) is a simulation-based validation method for systematically generating efficient test programs for exercising microarchitecture mechanisms. We present the relationship between high-level pipeline functionality for handling read-after-write (RAW) hazards and the design models derived in the BMV method. First, RAW failures are defined and classified into two categories based on the mechanism that is affected by a design error: pipeline interlock and result forwarding. Based on BMV models for the reservation station and the rename buffer, erroneous behaviors resulting in a pipeline interlock or a result forwarding failure can be mapped to a set of states in the models. Two theorems relating each failure class to BMV models for the reservation station and the rename buffer are derived and proved. The utility of the theorems is that they can be used to develop a RAW hazard simulator that is analogous to a single-stuck line fault simulator.