Achieved IPC Performance

  • Authors:
  • J. Liedtke;K. Elphinstone;S. Schiinberg;H. Hartig;G. Heiser;N. Islam;T Jaeger

  • Affiliations:
  • -;-;-;-;-;-;-

  • Venue:
  • HOTOS '97 Proceedings of the 6th Workshop on Hot Topics in Operating Systems (HotOS-VI)
  • Year:
  • 1997

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Abstract

Extensibility can be based on cross-address-space interprocess communication (IPC) or on grafting application-specific modules into the operating system. For comparing both approaches, we need to explore the best achievable performance for both models. This paper reports the achieved performance of cross-address-space communication for the L4 microkernel on Intel Pentium, Mips R4600 and DEC Alpha processors. The direct costs range from 45 cycles (Alpha) to 121 cycles (Pentium). Since only 2.3% of the L1 cache are required (Pentium), the average indirect costs are not to be expected much higher.