Itanium: a system implementor's tale

  • Authors:

  • Charles Gray;Matthew Chapman;Peter Chubb;David Mosberger-Tang;Gernot Heiser

  • Affiliations:

  • The University of New South Wales, Sydney, Australia;The University of New South Wales, Sydney, Australia and National ICT Australia, Sydney, Australia;The University of New South Wales, Sydney, Australia and National ICT Australia, Sydney, Australia;HP Labs, Palo Alto, CA;The University of New South Wales, Sydney, Australia and National ICT Australia, Sydney, Australia

  • Venue:
  • ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
  • Year:
  • 2005

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Abstract

Itanium is a fairly new and rather unusual architecture. Its defining feature is explicitly-parallel instruction-set computing (EPIC), which moves the onus for exploiting instruction-level parallelism (ILP) from the hardware to the code generator. Itanium theoretically supports high degrees of ILP, but in practice these are hard to achieve, as present compilers are often not up to the task. This is much more a problem for systems than for application code, as compiler writers' efforts tend to be focused on SPEC benchmarks, which are not representative of operating systems code. As a result, good OS performance on Itanium is a serious challenge, but the potential rewards are high. EPIC is not the only interesting and novel feature of Itanium. Others include an unusual MMU, a huge register set, and tricky virtualisation issues. We present a number of the challenges posed by the architecture, and show how they can be overcome by clever design and implementation.