Incremental ABV for functional validation of TL-to-RTL design refinement
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
A Schedulerless Semantics of TLM Models Written in SystemC Via Translation into LOTOS
FM '08 Proceedings of the 15th international symposium on Formal Methods
Reachability Problems in Piecewise FIFO Systems
ACM Transactions on Computational Logic (TOCL)
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In the design process of SoC (System on Chip), validationis one of the most critical and costly activity. The mainproblem for industrial companies like STMicroelectronics,stands in validation at the complete system level. At thislevel, the properties to verify concern the well behaviourcomposed of the different processes interconnected aroundthe system bus. In our work we consider the deadlock-freeproperty. In this paper we present an approach for deadlockdetection consisting in generating automatically a LOTOSdescription of the system. Then, by using CADP toolboxdeveloped at INRIA by the VASY team, the LOTOS descriptioncan then be used for the evaluation of temporal logicformulæ, either on-the-fly or after the generation of a LabelledTransition System (LTS). The automatic LOTOS codegeneration is decomposed in two parts, the code generationof the processes behaviour (work under progress) and thecode generation for the interconnection of processes on agiven SoC bus. This paper presents the principles of interconnectabstraction showing that deadlock detection has totake into account properties of the implemented communicationchannel, avoiding the possibility to build a generaldeadlock detection tool. The resulting principles are thenapplied on the STMicroelectronics proprietary SoC bus, theSTBus, leading in the development of the LOTOS code generationsoftware.