VIP: An FPGA-based Processor for Image Processing and Neural Networks

Authors:
Jocelyn Cloutier;Steven Pigeon;Francois R. Boyer;Eric Cosatto;Patrice Y. Simard
Affiliations:
-;-;-;-;-
Venue:
MICRONEURO '96 Proceedings of the 5th International Conference on Microelectronics for Neural Networks and Fuzzy Systems
Year:
1996

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Abstract

We present in this paper the architecture and implementation of the Virtual Image Processor (VIP) which is an SIMD multiprocessor build with large FPGAs. The SIMD architecture , together with a 2D torus connection topology, is well suited for image processing, pattern recognition and neural network algorithms. The VIP board can be programmed on-line at the logic level, allowing optimal hardware dedication to any given algorithm.