A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors

Authors:
R. Silvera;J. Wang;G. Gao;R. Govindarajan
Affiliations:
-;-;-;-
Venue:
PACT '97 Proceedings of the 1997 International Conference on Parallel Architectures and Compilation Techniques
Year:
1997

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Abstract

Several modern superscalar processors contain an out of order (OOO) instruction issue mechanism, which resolves dependencies between instructions to expose greater instruction level parallelism (ILP). How to extend a traditional instruction scheduler to take advantage of these hardware resources has presented both a challenge and an opportunity for compiler design. In this paper, we present a new approach for instruction scheduling, which reorders the instructions in a traditional instruction schedule to reduce its register pressure while maintaining the amount of ILP exploitable by the target OOO processor. This may prevent the introduction of spill code, thus producing a performance improvement. We have implemented our instruction scheduler under the MOST scheduling testbed. Our experiments show that the proposed approach reduces the register pressure by 12.81% in SPEC92 benchmark loops which do not require any spill code. For loops with a high register pressure, our approach reduced the amount of spill code required by an average of 32.08%, and produced an average performance improvement of 8.79%.