Register-sensitive selection, duplication, and sequencing of instructions
ICS '01 Proceedings of the 15th international conference on Supercomputing
IEEE Transactions on Computers
Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors
LCPC '99 Proceedings of the 12th International Workshop on Languages and Compilers for Parallel Computing
Studying compiler optimizations on superscalar processors through interval analysis
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
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The phase ordering of register allocation and instruction scheduling in a compiler and their integration have been well studied for in-order issue and VLIW processors. In this paper we study this problem in the context of out-of-order issue processors. Such a study is interesting as the dynamic instruction ordering and register renaming support mechanisms in out-of-order issue processors are similar in spirit to what the complex register allocation and instruction scheduling techniques do at compile-time.We evaluated four existing techniques, namely Postpass Scheduling, Prepass Scheduling, Parallel Interference Graph, and Integrated Prepass Scheduling methods. Our initial experimental results reveal that for o-o-o issue processors the focus should be on reducing the register pressure/spill code than exposing the parallelism at compiling time.