Communication and computation performance of the CM-5
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
Micro benchmark analysis of the KSR1
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
A distributed shared memory multiprocessor ASURA: memory and cache architecture
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
The directory-based cache coherence protocol for the DASH multiprocessor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Time-Division Optical Communications in Multiprocessor Arrays
IEEE Transactions on Computers
MASCOTS '94 Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems
An Architecture based on the Memory Mapped Node Addressing in Reconfigurable Interconnection Network
PAS '97 Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
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The Aizu supercomputer is a massively parallel system suited to the solution of virtual reality problems and the support of multimedia applications. It employs a highly parallel MIMD architecture using a conflict-free internetwork system. The scalable communication system consists of two networks: a pyramid network and a reconfigurable network using optical links. The Aizu Supercomputer has a cluster configuration and a shared memory. Each PE includes 113 SPECmark and one cluster is organized with 8 PEs. In the trial production, the supercomputer will include 1365 PEs with more than 100 GFlops at peak performance.