A distributed shared memory multiprocessor ASURA: memory and cache architecture

  • Authors:
  • S. Mori;H. Saito;M. Goshima;S. Tomita;M. Yanagihara;T. Tanaka;D. Fraser;K. Joe;H. Nitta

  • Affiliations:
  • Dep. of Information Science, Faculty of Engineering, Kyoto University, Sakyo-ku, Kyoto, 606-01 Japan;Dep. of Information Science, Faculty of Engineering, Kyoto University, Sakyo-ku, Kyoto, 606-01 Japan;Dep. of Information Science, Faculty of Engineering, Kyoto University, Sakyo-ku, Kyoto, 606-01 Japan;Dep. of Information Science, Faculty of Engineering, Kyoto University, Sakyo-ku, Kyoto, 606-01 Japan;KUBOTA Corporation, 2-47, Shikitsuhigashi 1-chome, Naniwa-ku, Osaka, 556-91 Japan;KUBOTA Corporation, 2-47, Shikitsuhigashi 1-chome, Naniwa-ku, Osaka, 556-91 Japan;KUBOTA Corporation, 2-47, Shikitsuhigashi 1-chome, Naniwa-ku, Osaka, 556-91 Japan;KUBOTA Corporation, 2-47, Shikitsuhigashi 1-chome, Naniwa-ku, Osaka, 556-91 Japan;KUBOTA Corporation, 2-47, Shikitsuhigashi 1-chome, Naniwa-ku, Osaka, 556-91 Japan

  • Venue:
  • Proceedings of the 1993 ACM/IEEE conference on Supercomputing
  • Year:
  • 1993

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Abstract