An ASIC implementation of low power and high throughput blowfish crypto algorithm
Microelectronics Journal
Impact of high-level transformations within the ROCCC framework
ACM Transactions on Architecture and Code Optimization (TACO)
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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Nowadays, higher demand and greater awareness on security problems lend to the study of more secure, high performance, reliable and flexible systems. To meet these demands the implementation of the Blowfish algorithm in the commercial FPGA coprocessor microEnable has been chosen to present the high performance of such FPGA based reconfigurable systems. In this paper we demonstrate, how such a system can be used to enhance the speed of cryptographic computation dramatically. We show that by using this FPGA design the Blowfish computation can be increased in speed almost by a factor of 10. The achieved results lead to the general conclusion that the use of an FPGA coprocessor is ideally suited for the execution of cryptographic algorithms regarding to execution time and flexible usage.