The PowerPCTM 604 Microprocessor Design Methodology
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Validating the Itanium 2 Exception Control Unit: A Unit-Level Approach
IEEE Design & Test
An incremental learning framework for estimating signal controllability in unit-level verification
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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Design verification engineers are one of the hottest commodities in microprocessor design. The increased complexity of these chips has not been accompanied by an equal increase in design verification techniques. Thus, the existing work force must work smarter in order to make up the difference. This paper outlines one of the areas in which verification engineers at the Somerset Design Center have been able to do just that. By taking blocks of designs that have been entered early, and creating a unit-level simulation environment, the authors are able to do large amounts of testing (sometimes exhaustive) before the whole chip has been designed. This has contributed significantly to cutting down the time it takes to run functional simulations for the whole chip since most of the problems found at this point are interface problems. The test cases created for the unit-level simulations are then rerun at the chip-level in order to provide full confidence of quality. Although it is hard to exactly quantify the total impact on the time to market of any product, it is evident that the described techniques save resources and time.