Functional verification methodology for the PowerPC 604 microprocessor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Introducing the IA-64 Architecture
IEEE Micro
Itanium 2 Processor Microarchitecture
IEEE Micro
Divide and Conquer Approach to Functional Verification of Powerpc Microprocessors
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
SCS '04 Proceedings of the 9th Australian workshop on Safety critical systems and software - Volume 47
An incremental learning framework for estimating signal controllability in unit-level verification
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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As modern microprocessor designs become increasingly complex, certain units often receive less coverage than others during full-chip functional verification. A stable RTL model does not necessarily indicate that all units are equally stable. The authors illustrate the need for unit-level functional verification and present an effective methodology for verifying the XPN unit in the Itanium 2 microprocessor.