A comparison of MPCP and MSRP when sharing resources in the Janus multiple-processor on a chip platform

  • Authors:
  • Paolo Gai;Marco Di Natale;Giuseppe Lipari;Alberto Ferrari;Claudio Gabellini;Paolo Marceca

  • Affiliations:
  • -;-;-;-;-;-

  • Venue:
  • RTAS '03 Proceedings of the The 9th IEEE Real-Time and Embedded Technology and Applications Symposium
  • Year:
  • 2003

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Abstract

The new generation of embedded systems for automotiveapplications can take advantage of low-cost multiprocessorsystem-on a chip architectures. The real-time softwareapplications running on these systems require real-timeprocessor scheduling, and also require the managementof the communication and synchronization of tasksexecuting on different processors with limited blockingtime. Conventional real-time technologies, like the RateMonotonic scheduling algorithm together with the MultiprocessorPriority Ceiling Protocol (MPCP) can be usedto this purpose. In earlier work, we proposed the MultiprocessorStack Resource Policy (MSRP) for scheduling tasksand sharing resources in multiprocessor on a chip architectures.In this paper we present an experimental evaluationthat compares the performance of our algorithm witha solution based on Rate Monotonic and MPCP in the contextof the Janus multiple processor architecture. The evaluationof the algorithm has been triggered by our ongoingresearch in the automotive domain. We report on two setsof experiments: the first addresses a range of generic taskconfigurations to see if one of the algorithms can clearlyoutperform the other. The results show MSRP to be betterfor random task periods but are probably not conclusive.Later, we focus on a more application-specific (also morerestrictive) architecture design representing a typical automotiveapplication: a power-train controller. In this case,MSRP clearly performs better. The performance gap betweenthe two policies can be further increased when consideringthat MSRP is much simpler to implement, it has alower overhead, and it allows RAM memory optimization.