A fast-multiplier generator for FPGAs

Authors:
S. Kumar;K. Forward;M. Palaniswami
Affiliations:
-;-;-
Venue:
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Year:
1995

Citing 1
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Abstract

FPGA implementation of artificial neural networks calls for multipliers of various word length. In this paper, a new algorithm for generating variable word length multipliers for FPGA implementation is presented. The multipliers generated are based on a Booth Encoded optimized Wallace tree architecture. Several features of FPGA architecture are used to generate fast and efficient multipliers. These multipliers are shown to be 20% faster than existing FPGA multiplier implementations.