Resource requirements for field programmable interconnection chips

Authors:
D. Bhatia;J. Haralambides
Affiliations:
-;-
Venue:
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Year:
1995

Citing 2
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Introduction to parallel algorithms and architectures: array, trees, hypercubes

Introduction to parallel algorithms and architectures: array, trees, hypercubes
A Permutation Network

Journal of the ACM (JACM)

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Abstract

In this paper we prove an /spl Omega/(n log n) lower bound on the number of edges of an n-permutation graph G=(V, E). The lower bound is applicable to and characterizes permutations for Field Programmable Interconnection Chips and, more importantly, permutation networks in general. We also propose a family of permutation networks as a variation of the known Benes network with a wide range of diameters, a network property directly related to routing delays. Finally, the relation between the total number of programmable switches and the routing delay (maximum length of routing paths for specific I/O permutations) is explored.