Challenges in Low Power Microprocessor Design

  • Authors:

  • Suresh Rajgopal

  • Affiliations:

  • -

  • Venue:
  • VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
  • Year:
  • 1996

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Abstract

This paper addresses the challenge of controlling power dissipation in the microprocessor domain. Power efficiency in microprocessors is achieved not as much by by low watts, but more by increaed SpecInt/Watt. With process and voltage gains often being offset by increased frequency targets, reducing wasted power is becoming the theme in design. In this paper we address the challenges of performing low-power high-performance design. First we evaluate known low-power techniques, outlining design concerns and describing areas of maximum impact. Then we introduce the notion of benchmarks for power describing their relevance in system design as well as in power reduction.