Design of a VLSI Hardware PET Decoder

Authors:
G. Ascia;V. Catania;G. Ficili
Affiliations:
-;-;-
Venue:
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Year:
1997

Citing 3
Cited 0

MPEG: a video compression standard for multimedia applications

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PET—priority encoding transmission (video): a new, robust and efficient video broadcast technology

Proceedings of the third ACM international conference on Multimedia
Priority encoding transmission

SFCS '94 Proceedings of the 35th Annual Symposium on Foundations of Computer Science

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Abstract

In this paper we present the design of a hardware architecture for real-time PET (Priority Encoding Transmission) decoding of MPEG-1 messages. The main features of the decoder are: pipeline architecture and parallelism in the execution of some critical phases in the decoding process. The estimated clock frequency is 50 MHz with a required silicon area of about 35 mm2. The total latency introduced to decode an MPEG-1 GOP made up of 30 frames, each of 320X240 pixels, is about 40 ms.