Microprocessor design verification
Journal of Automated Reasoning
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Symbolic Model Checking
Proceedings of the 8th International Conference on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Experiments in Theorem Proving and Model Checking for Protocol Verification
FME '96 Proceedings of the Third International Symposium of Formal Methods Europe on Industrial Benefit and Advances in Formal Methods
An Integration of Model Checking with Automated Proof Checking
Proceedings of the 7th International Conference on Computer Aided Verification
Modular Verification of SRT Division
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
The Murphi Verification System
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
WIFT '95 Proceedings of the 1st Workshop on Industrial-Strength Formal Specification Techniques
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The past decade has seen tremendous progress in the application of formal methods for hardware design and verification. While a number of different techniques based on BDDs, symbolic simulation, special-purpose decision procedures, model checking, and theorem proving have been applied with varying degrees of success, no one technique by itself has proven to be effective enough to verify a complex register-transfer level design, such as a state-of-the-art microprocessor. To scale up formal verification to industrial-scale designs it is necessary to combine these complimentary techniques within a general logical environment that can support appropriate abstraction mechanisms. The Prototype Verification System (PVS) is an environment to support the exploration of such a combined approach to verification. PVS is designed to exploit the synergies between language and deduction, automation and interaction, and theorem proving and model checking. This paper gives an overview of PVS and describes some of the major applications of PVS.