Asynchronous Implementation of Synchronous Esterel Specifications

Authors:
Raj S. Mitra;Bishnupriya Bhattacharya;Luciano Lavagno
Affiliations:
-;-;-
Venue:
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Year:
1997

Citing 4
Cited 0

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Abstract

The synchrony hypothesis of Esterel demands the generation of a single monolithic FSM from the specifications. However, for large specifications, the size of this FSM can prove to be inhibitively large. In this paper, we propose a practical solution to this problem, which generates separate FSMs for each of the concurrent instructions. We also enumerate the deviations in semantics due to this translation algorithm, so that the user is aware of the executable semantics that he should expect.