FPGA Implementation of Median Filter

Authors:
R. Maheshwari;S. S. S. P. Rao;E. G. Poonach
Affiliations:
-;-;-
Venue:
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Year:
1997

Citing 0
Cited 4

Cost-effective video filtering solution for real-time vision systems

EURASIP Journal on Applied Signal Processing
A Comparison Study for a Neural Network Based Embedded Appliance

Proceedings of the 2011 conference on Neural Nets WIRN10: Proceedings of the 20th Italian Workshop on Neural Nets
ARM based microcontroller for image capturing in FPGA design

ISVC'05 Proceedings of the First international conference on Advances in Visual Computing
VLSI implementation of star detection and centroid calculation algorithms for star tracking applications

Journal of Real-Time Image Processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper gives the algorithm and implementation details of a sliding real time 3/spl times/3 median filter. The design is implemented on a Xilinx XC4010 FPGA chip. It is tested and integrated at ER&DC, Trivandrum. The design is tailored to exploit certain features of sliding windows. The Algorithm used to implement median filter is very efficient and implementation results show the significant improvements in operating frequency and hardware requirements over general purpose techniques.