The Stanford FLASH multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
The Murphi Verification System
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
IWTCS Proceedings of the IFIP TC6 11th International Workshop on Testing Communicating Systems
Formal verification of the HAL S1 System cache coherence protocol
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
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Directed tes program-based verification or formal verification methods are usually quite ineffective on large cache-coherent, non-uniform memory access (CC-NUMA) multi-processors because of the size and complexity of the design and the complexity of the cache-coherence protocol. A controllable biased/constrained random stimuli generator coupled with an error detection mechanism using scoreboards and feedback with coverage analysis tools is a promising alternative methodology. We applied this methodology to verify a shared memory and message passing multiprocessor system consisting of 32 and 64 bit processor-based symmetric multiprocessing (SMP) servers connected by a proprietary cache coherent router-based interconnect fabric. This paper describes the problems faced, solutions implemented, and design decisions taken to design the scoreboard and discusses the errors found by this methodology.