VLSI Architecture for a Flexible Motion Estimation with Parameters

Authors:
Jinku Choi;Masao Yanagisawa;Tatsuo Ohtsuki;Nozomu Togawa
Affiliations:
Department of Electronic, Information and Communication Engineering Waseda University, 3-4-1 Okubo, Shinju-ku, Tokyo 169-8555, Japan;Department of Electronic, Information and Communication Engineering Waseda University, 3-4-1 Okubo, Shinju-ku, Tokyo 169-8555, Japan;Department of Electronic, Information and Communication Engineering Waseda University, 3-4-1 Okubo, Shinju-ku, Tokyo 169-8555, Japan;Department of Information and Media Sciences, The University of Kitakyushu, 1-1 Hibikino, Wakamatsu-ku, Kitakyushu 808-0135, Japan
Venue:
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Year:
2002

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Abstract

If motion estimation can choose the most suitable algorithm according to the changing characteristics of input image signals, we can get benefits, which improved quality and performance, reduced power consumption, and an optimized system. In this paper, we propose a reconfigurable approach to motion estimation algorithm. Our algorithm determines motion type and then selects adapted algorithm in order to improve quality and performance of images. We implemented the flexible and reconfigurable hardware architecture by hardware with address generator unit, delay unit, and parameters. Our architecture supports more than one block-matching algorithms and parameters providing to optimize system. We are implementing our architecture by using hardware description language (VHDL) and synthesis design tools. We analyze the performance of the architecture and present adaption to algorithm for a low cost real time application.