Register Transfer Operation Analysis during Data Path Verification

Authors:
D. Sarkar
Affiliations:
Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, India
Venue:
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Year:
2002

Citing 7
Cited 1

Automatic Verification of Sequential Circuits Using Temporal Logic

IEEE Transactions on Computers
Mechanizing Verification of Arithmetic Circuits: SRT Division

Proceedings of the 17th Conference on Foundations of Software Technology and Theoretical Computer Science
A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio

CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Automated RTL Verification Based on Predicate Calculus

CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Status Condition Analysis during Data Path Verification of Sequential Circuits

VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Formal verification of the AAMP5 microprocessor: a case study in the industrial use of formal methods

WIFT '95 Proceedings of the 1st Workshop on Industrial-Strength Formal Specification Techniques
Verification of Tempura specification of sequential circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Verification method of dataflow algorithms in high-level synthesis

Journal of Systems and Software

Quantified Score

Hi-index	0.00

Visualization

Abstract

A control part - data path partition based sequential circuit verification scheme aimed at avoiding state explosion comprises two major modules namely, a data path verifier and a control part verifier. The functional specifications of these modules have been identified. Of the two broad tasks involved in data path verification, namely status condition analysis and register transfer operation analysis, a method for the second task along with its termination, soundness and completeness have been treated rigorously. Its performance on some data path architectures has been reported.