A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment

• Authors: Debapriya Sahu
• Venue: ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
• Year: 2002

This paper describes the PLL designed for the analog front-end of the silicon tuner in the cable modem system. The PLL is used to generate clocks (150-175MHz) for the DAC and hence the phase noise (jitter) requirement is very aggressive (15ps rms, which is less than 1 degree of integrated phase error). Low noise design for all the main blocks was a key to achieve this. Care was taken to reduce reference spurs and supply/substrate injected spurs. The PLL uses two supplies. Charge pump and voltage controlled oscillator (VCO) work off a 3.3V analog supply as it can give maximum VCO control voltage compliance, which helps reduce VCO gain, and hence reference and supply/substrate induced spurs. The digital part works off 1.8V supply as 1.8V core transistors give fastest switching which reduces phase noise in the dividers. The 3.3V to 1.8V interfaces have been optimized for the desired edges of output clock and phase comparison clock so that they have minimum contribution to phase error. Optimum loop bandwidth, PSRR and supply filtering were achieved to minimize phase noise and spurious modulation. The reference spur has been reduced by minimizing charge and clock feedthrough in the charge pump, and using a fourth order loop filter. The VCO is a differential current-starved ring oscillator. The VCO stages have large signal swing and large Gm to minimize the phase noise.