Graph Transformations for Improved Tree Height Reduction

  • Authors:
  • G. N. Mangalam;Sanjiv Narayan;Paul van Besouw;LaNae Avra;Anmol Mathur;Sanjeev Saluja

  • Affiliations:
  • -;-;-;-;-;-

  • Venue:
  • VLSID '03 Proceedings of the 16th International Conference on VLSI Design
  • Year:
  • 2003

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Abstract

Tree height reduction helps in minimizing thecritical path delay and area in datapath rich designs duringsynthesis. We introduce in this paper, the necessary conditions to identify height reducible arithmetic expressions andthree graph transformations that make Tree Height Reduction more efficient: (a) Bit-width matching - a techniquein which input signals that match in their bit-widths aregrouped together so that smaller width arithmetic nodesare created in the graph. (b) Carry / Borrow Optimization - a graph transformation by which an optimum numberof single bit inputs are distributed as carry / borrow to theadd / subtract nodes in the graph. (c) Constant grouping - agraph transformation in which constant inputs are groupedtogether to form a sub-tree of constants. Experiments onindustrial designs with these graph transformations coupledwith Tree Height Reduction have shown significant improvement in critical path delay and area.