A self-driven test structure for pseudorandom testing of non-scan sequential circuits

  • Authors:

  • F. Muradali;J. Rajski

  • Affiliations:

  • -;-

  • Venue:
  • VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
  • Year:
  • 1996

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Abstract

Introduced is a self-driven test point structure which permits at-speed, on-chip, non-scan, sequential testing using parallel pseudorandom test patterns applied only to the primary inputs of the circuit under test. The test network is unique in that aside from a test mode flag, all I/O signals needed for test system operation are tapped from within the circuit itself. High single stuck-at fault coverage is achieved for a number of ISCAS-89 benchmarks.