Optimized wafer-probe and assembled package test design for analog circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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It is well known that wafer probe test costs of analogICs are an order of magnitude less than thecorresponding test costs of assembled packages. It istherefore natural to push as much as the testing processinto wafer-probe test as possible while limiting the scopeof assembled package test. However, the signal drive andresponse observation capabilities during wafer probe testare limited in comparison to assembled package test. Inthis paper, it is shown that by marginally increasing thecapabilities of wafer probe test equipment to include low-speedtransient signals, significant numbers of bad ICscan be detected early during wafer probe test. Theoptimal test stimulus is determined by co-optimizing thewafer-probe and assembled package test waveforms.Overall, test costs, including the cost of packaging badICs are minimized.