Numerical recipes in C (2nd ed.): the art of scientific computing
Numerical recipes in C (2nd ed.): the art of scientific computing
Analytical fault modeling and static test generation for analog ICs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Fault-based automatic test generator for linear analog circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Minimal length diagnostic tests for analog circuits using test history
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
Analog Testing with Time Response Parameters
IEEE Design & Test
An Integrated Approach for Analog Ciruit Testing with a Minmum Number of Detected Parameters
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Test Vector Generation for Linear Analog Devices
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
A novel test generation approach for parametric faults in linear analog circuits
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
7.2 Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Test Generation for Accurate Prediction of Analog Specifications
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Substrate Testing on a Multi-Site/Multi-Probe ATE
Journal of Electronic Testing: Theory and Applications
Wafer-level defect screening for "big-D/small-A" mixed-signal SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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It is well known that wafer-probe test costs of analog ICs are an order of magnitude less than the corresponding test costs of assembled packages. It is therefore natural to push as much of the testing process into wafer-probe testing as possible to reduce the scope of assembled package testing. However, the signal drive and response observation capabilities during wafer probe testing are limited in comparison to assembled packages. In this article, it is shown that by using band-limited transient test signals, which can be supported by wafer-probe test instrumentation, significant numbers of bad ICs can be detected early during the wafer-probe test. The optimal test stimuli are determined by cooptimizing the wafer-probe and assembled package test waveforms. Overall test costs, including the cost of packaging bad ICs, are minimized and are reduced up to four times. The proposed method has been validated using hardware test data, which were obtained through measurements made on a prototype.