PASTE '01 Proceedings of the 2001 ACM SIGPLAN-SIGSOFT workshop on Program analysis for software tools and engineering
L1 data cache decomposition for energy efficiency
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Energy-efficient instruction cache using page-based placement
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Partitioned instruction cache architecture for energy efficiency
ACM Transactions on Embedded Computing Systems (TECS)
SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
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In this paper, we model and evaluate the energy consumption of three different multiple access cache architectures that target the reduction of access latencies of associative caches. Further, we compare their energy consumption with that of traditional direct-mapped and set-associative caches. Among all the cache architectures, the most recently used cache is found to be most energy-efficient for all studied benchmarks and configurations. We also evaluated the influence of compiler optimizations on the energy saving of different cache architectures and find that compiler optimization can significantly reduce the memory system energy across all cache architectures. However, the most aggressive optimizations do not necessarily lead to the most energy-efficient code. We also find that the optimizations always reduce the energy consumed due to instruction accesses for the Mediabench benchmark suite unlike the energy consumed by the data accesses.