An FPGA Implementation of a Flexible, Parallel Image Processing Architecture Suitable for Embedded Vision Systems

Authors:
Stephanie McBader;Peter Lee
Affiliations:
-;-
Venue:
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Year:
2003

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Abstract

This paper describes the design of a programmable parallel architecture that is to be used for signal preprocessing in intelligent embedded vision systems. The architecture has been implemented and tested using a Celoxica RC1000 Prototyping Platform with a Xilinx XCV2000E FPGA. The system operates at a clock rate of 50 MHz and can perform preprocessing functions such as filtering, correlation and transformation on an image of 256x256 pixels at up to 667 frames/s.