Pfinder: Real-Time Tracking of the Human Body
IEEE Transactions on Pattern Analysis and Machine Intelligence
Sequential Operations in Digital Picture Processing
Journal of the ACM (JACM)
Learning Patterns of Activity Using Real-Time Tracking
IEEE Transactions on Pattern Analysis and Machine Intelligence
Non-parametric Model for Background Subtraction
ECCV '00 Proceedings of the 6th European Conference on Computer Vision-Part II
W4: Who? When? Where? What? A Real Time System for Detecting and Tracking People
FG '98 Proceedings of the 3rd. International Conference on Face & Gesture Recognition
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Finding Connected Components in Digital Images
ITCC '01 Proceedings of the International Conference on Information Technology: Coding and Computing
Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Graph Cuts and Efficient N-D Image Segmentation
International Journal of Computer Vision
AVSS '09 Proceedings of the 2009 Sixth IEEE International Conference on Advanced Video and Signal Based Surveillance
Detecting moving objects, ghosts, and shadows in video streams
IEEE Transactions on Pattern Analysis and Machine Intelligence
Journal of Signal Processing Systems
Real-time video surveillance on an embedded, programmable platform
Microprocessors & Microsystems
Hi-index | 0.00 |
This paper demonstrates the use of a single-chip FPGA for the segmentation of moving objects in a video sequence. The system maintains highly accurate background models, and integrates the detection of foreground pixels with the labelling of objects using a connected components algorithm. The background models are based on 24-bit RGB values and 8-bit gray scale intensity values. A multimodal background differencing algorithm is presented, using a single FPGA chip and four blocks of RAM. The real-time connected component labelling algorithm, also designed for FPGA implementation, run-length encodes the output of the background subtraction, and performs connected component analysis on this representation. The run-length encoding, together with other parts of the algorithm, is performed in parallel; sequential operations are minimized as the number of run-lengths are typically less than the number of pixels. The two algorithms are pipelined together for maximum efficiency.