Loop Dissevering: A Technique for Temporally Partitioning Loops in Dynamically Reconfigurable Computing Platforms

Authors:
João M. P. Cardoso
Affiliations:
-
Venue:
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Year:
2003

Citing 0
Cited 7

Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations

IEEE Transactions on Computers
Temporal Partitioning to Amortize Reconfiguration Overhead for Dynamically Reconfigurable Architectures

IEICE - Transactions on Information and Systems
Configuration Sharing to Reduce Reconfiguration Overhead Using Static Partial Reconfiguration

IEICE - Transactions on Information and Systems
Task graph scheduling for reconfigurable architectures driven by reconfigurations hiding and resources reuse

Proceedings of the 19th ACM Great Lakes symposium on VLSI
An ILP formulation for the task graph scheduling problem tailored to bi-dimensional reconfigurable architectures

International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
Multiloop parallelisation using unrolling and fission

International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
An operation and interconnection sharing algorithm for reconfiguration overhead reduction using static partial reconfiguration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a technique, called loop dissevering, to temporally partitioning any type of loop presented in programming languages. The technique can be used in the presence of complex loops that oversize the physically available hardware resources. Unlike loop fission or distribution, the technique can be applied to all types of loops and it is not constrained by loop dependences. Thus, the technique guarantees the compilation of complex loops that otherwise cannot be mapped to the target reconfigurable computing architecture. Moreover, the technique only needs to communicate scalar variables between temporal partitions (configurations) and does not need auxiliary array variables used for scalar expansion when applying loop distribution.We show results of applying the technique when compiling C programs to the PACT eXtreme Processing Platform (XPP) and to a hypothetical version with faster switching between contexts. We show that the technique leads to implementations using fewer resources and might lead to performance improvements when it is possible to overlap some of the execution stages (e.g., fetch, configure, and compute). As performance is concerned, the technique is as most efficient as fast is the reconfiguration time.