BIST for Phase-Locked Loops in Digital Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Jitter Testing for Gigabit Serial Communication Transceivers
IEEE Design & Test
A High-Resolution Jitter Measurement Technique Using ADC Sampling
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testing Gigabit Multilane SerDes Interfaces with Passive Jitter Injection Filters
ITC '01 Proceedings of the 2001 IEEE International Test Conference
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The rapid deployment of Gigabit differential signal I/Obuffers in ASICs and other ICs for systems such asSONET, Firewire, Ethernet, and Fiber Channel ispresenting several challenges for testing. At the presenttime, testing the functionality of these ICs can only bedone by using expensive stand-alone bit-error-rate test sets.The excessive test time and cost makes this approachimpossible for volume production. On the other hand, theindustrial trend for higher level of integration means thatGigabit serial ports can be used as a standard I/O macro forany IC. There is an urgent need for Automatic TestEquipment (ATE) manufacturers to design multi-port,differential instruments and integrate them into testsystems, including control software. In this article, as anextension to the challenges that we listed in the 1999International Technology Roadmap for Semiconductors[1], we will discuss the impact on ATE architecture inorder to accommodate multi-Gb/s serialcom tests, such asembedded clock recovery circuit testing, asynchronoustesting, jitter generation/tolerance/transfer testing etc. Wewill describe what it takes to extend a conventional ATE'scapability for testing multiple Giga-bit-per-second (Gb/s)SerDes (Serializer/Deserializer), and how the throughputcan be improved.